The present invention generally relates to a bias-generating integrated circuit for optimally generating a voltage to bias cascode transistors, wherein biasing sets the operating point of a cascode transistor and a signal transistor being cascoded in a circuit in order to precisely control its small signal characteristics, such as its transconductandance and impedance.
Cascode transistors often exist in analog circuits such as amplifiers, voltage regulators, and current mirrors. For example, transistor 13 in subsequently described in FIG. 1E is the cascode transistor, and transistor 14 is referred to as the “signal transistor” being cascoded. Cascode transistors may be used to increase the gain of a signal transistor amplifier, protect or shield the signal transistor, reduce Miller effect, and/or increase output resistance. Bias circuitry for such a cascode transistor is generally optimal if it is both physically small and capable of providing a voltage bias value that is fairly constant, and also is capable of “tracking” the performance of the cascode transistor. The performance of the cascode transistor will vary over technology processes and/or over operating conditions. The large variation in performance of a circuit such as an amplifier is exacerbated when the cascode transistors and the signal transistors are of different “technology types”. Therefore, the bias circuitry for the cascode transistor should effectively “track” characteristics not only of the cascode transistor, but also characteristics of the signal transistor. Integrated circuits often are fabricated using integrated circuit technologies which include multiple types of transistors to meet different performance conditions. For example, in the case of a MOSFET cascode transistor of a particular technology type, its gate voltage bias must be in a certain range for both the cascode transistor and the signal transistor of a different technology type to remain turned on properly over all expected operating conditions and process variations.
Some prior art bias voltage circuits include one or more diode-connected transistors and/or transistor voltage dividers where all of the transistors are of the same technology type.
The value of the bias voltage generated may vary widely over various integrated circuit operating conditions, such as over a wide temperature range, and/or over a wide range of integrated circuit fabrication process variations, and/or over a wide range of power supply voltage variations. Moreover, the prior art does not optimally provide bias voltages for multiple technology types of transistors.
Many integrated circuit (IC) technologies include multiple kinds of transistors. For example, applications involving high voltage power supplies such as for voltage regulators, power amplifiers, or for DSL and video applications it is typical to use an IC technology containing multiple kinds of transistors, for example transistors having different drain-source breakdown voltages, i.e. VDS breakdown voltages in the case of MOSFET transistors. The “signal transistors” which are intended to rapidly pass the signal being amplified usually have lower VDS breakdown voltages, whereas the associated cascode transistors may have very high VDS breakdown voltages so that a system including such transistors can tolerate the high power supply voltage and effectively protect the associated signal transistor from damage. Different “technology types” of transistor within a particular IC technology also have been used in low voltage integrated circuit applications, such as in wireless communication applications. For example, a low voltage integrated circuit chip may be manufactured using a technology which provides two different technology types of MOSFETs, one with a typical threshold voltage VT of approximately 300 millivolts and the other with a threshold voltage near zero volts.
The prior art methods of generating a bias voltage include using a single transistor in a diode configuration. For example, for applications in high voltage systems the cascode transistor needs to be biased with a large voltage, so the biasing diode-connected transistor needs to have its gate length L quite large compared to its gate width W, wherein its W/L ratio becomes non-optimally small. (The terms “gate length” and “gate width” of a field effect transistor are also commonly referred to as its “channel length” and “channel width”, respectively, even though the channel length is not exactly identical to the gate length. The terms “gate length” and “gate width” as used in the claims are intended to encompass the terms “channel length” and “channel width”, respectively.) Such cascode transistors generate bias voltages that tend to vary widely with respect to circuit performance, and also become non-optimal with respect to integrated circuit layout efficiency. If use of the VGS voltage (i.e., gate-to-source voltage) of a single connected transistor or diode-connected transistor is insufficient to provide the needed bias voltage magnitude, then the bias voltage generating circuitry may need to utilize a “stack” of connected transistors or diode-connected transistors to obtain the needed large bias voltage. Or, transistors may be used in conjunction with resistive voltage divider circuits as another way to generate adequately large bias voltages. In all such cases, the generated bias voltages typically vary widely with integrated circuit process parameters, power supply voltage variations, and temperature variations. The longer the stack or string of elements, the greater the variation because of non-ideal behaviors of each individual component within the stack. Therefore, the generated bias voltages typically do not optimally follow or “track” the VGS or VDS voltages generated by transistors contained within the bias voltage generating circuitry. Furthermore, under these conditions the prior art bias voltage generating circuitry is physically larger than is desirable and therefore increases manufacturing costs.
The foregoing variation of generated bias voltage is exacerbated when a cascode circuit (or other circuit) being biased by the generated bias voltage contains multiple types of transistors, meaning, for example, that the different transistors within the same integrated circuit are manufactured using different designed-in doping levels, oxide thicknesses, etc., yielding different intrinsic properties such as breakdown voltage and threshold voltage. The different types of transistors referred to herein as being of different “technology types” may have substantially different intrinsic properties and performance trends over chip temperature and integrated circuit manufacturing process parameters.
Following are some specific examples of prior art bias voltage generating circuits:
FIG. 1A shows conventional bias circuitry including diode-connected transistors used for generating bias voltages VBIAS1 and VBIAS2 and is especially useful for biasing N-channel cascode transistors and P-channel cascode transistors, respectively. VBIAS1 is equal to the VGS voltage of a diode-connected N-channel MOSFET 3 having its source connected to the lower supply voltage VEE and its gate and drain connected to a conductor to a bias current source IB1, and similarly for VBIAS2. However, the diode bias circuit of FIG. 1A has the gate width and gate length shortcomings described above, and being a single transistor, it cannot track cascode circuit systems containing different technology types of transistors.
FIG. 1B illustrates another known bias circuit 5 which generates a bias voltage VBIAS using two (or more) “stacked” diode-connected N-channel transistors 6 and 7 coupled in series with a bias current source IB. Therefore, VBIAS is equal to the sum of the VGS voltages of the stacked diode-connected transistors 6 and 7, and may produce a bias voltage, equal to the sum of two threshold voltages (VT's), which is too large in value.
FIG. 1C shows a conventional bias circuit 8 which generates a bias voltage VBIAS that is equal to a non-integer multiple of the VGS voltage of N-channel transistor 9. Resistor R1 is connected between the gate of transistor 9 and VEE, and resistor R2 is connected between the gate and drain of transistor 9, the source of which is connected to VEE. However, the bias circuit of FIG. 1C, or any bias voltage generator including resistors and transistors, has the shortcomings of not tracking cascode transistor and signal transistors well, since the characteristics of a resistor are very different from those of a transistor.
FIG. 1D illustrates a known “composite” transistor 11 (shown in FIG. 2.14 of the subsequently cited Enz and Vittoz reference). In composite transistor 11, N-channel transistors 11A and 11B are connected in series, wherein the gates of transistors 11A and 11B both are connected to the drain of transistor 11A, the source of transistor 11B being coupled to VEE. Transistors 11A and 11B are biased in a “weak inversion” region in order produce a PTAT reference voltage, i.e., a reference voltage which is proportional to the absolute temperature. However, the shortcoming is that many applications do not require PTAT voltages and this composite transistor is not useful for biasing cascode transistors and will not track the cascoded circuitry, which is typically operated in the strong inversion region. However, the Enz and Vittoz reference disclose the FIG. 1D configuration in the strong inversion region for a different purpose, to generate fractional pinch-off voltages (Vdsat), and use all the same technology type of transistors. This purpose is unrelated to that of the present invention. Also, optimal transistor gate sizes determined in accordance with the Enz and Vittoz teachings are not optimal for the purposes of the present invention.
FIG. 1E shows a bias circuit wherein a known “composite” transistor 12 includes a suitable number of N-channel transistors coupled in series between VEE and a conductor 13A. This circuit is shown in FIG. 2.22 of the Enz and Vittoz reference. Conductor 13A is connected to one terminal of a bias current source IB and also to the gate of a N-channel cascode transistor 13. The multiple transistors of composite transistor 12 typically all are biased in a strong inversion state, and all have the same gate-width-to-gate-length ratio (W/L ratio), which is equal to the W/L ratio of cascode transistor 13. The source of cascode transistor 13 is connected to the drain of a signal transistor 14 having its source connected to VEE and having its input connected to an input signal. The bias circuit of FIG. 1E has the shortcomings of being composed of all the same kind of transistors and is intended to generate the lowest voltage on conductor 13A that would keep the cascode system 13 and 14 active. Also, optimal transistor gate sizes determined for the composite transistor of FIG. 1E are not optimal for the purposes of the invention subsequently described herein.
The Galup-Montoro et al. article cited below describes a composite MOSFET (metal oxide semiconductor field effect transistor) which consists of the series connection of two transistors, as in the present invention, for example the composite transistor in subsequently described FIG. 2A. However, the composite transistor described in the Galup-Montoro et al. article has been used in low-voltage, high-frequency analog circuits. The two transistors in the Gallup-Montoro et al. composite transistor both are of the same technology type, and are not sized the same as in the present invention, nor are they used for the same purpose.
The following references provide further background:    (1) T. C. Choi, et al., “High frequency CMOS switched capacitor filters for communications applications”, JSSC. Vol. SC-18, pp. 652-664. December 1983    (2) C. C. Enz and E. A. Vittoz, “Tutorial: CMOS Low-Power Analog Circuit Design”, chapter 1.2. ISCAS, Atlanta, May 1996.    (3) R. Gregorian, “Introduction to CMOS Opamps and Comparators”, Wiley & Sons. 1999.    (4) P. E. Allen, D. R. Holberg, “CMOS Analog Circuit Design,” Oxford University Press. 1987.    (5) Galup-Montoro et al., “Series-Parallel Association of FET's for High Gain and High-Frequency Applications”, IEEE Journal of Solid-State Circuits, vol. 29, no. 9, September, 1994.
It should be noted that in the above described prior art, the N-channel transistors of the bias voltage generator circuitry and the cascode circuitry biased thereby all are of the same technology type. Also, the P-channel transistors of the bias voltage generator circuitry and the circuitry biased thereby all are of the same technology type.
It is generally recognized that use of small, single MOSFETs in a bias voltage generator circuit has the drawback that if the transistor gate width W is made too small relative to the W/L ratio, to both save chip area and provide large bias voltages, then the generated bias voltage tends to vary more with respect to temperature, integrated circuit processing parameters, and power supply voltages.
Thus, there is an unmet need for high voltage integrated circuit bias voltage generating circuitry that is suitable for optimum biasing of cascode transistor circuitry including transistors of different technology types.
There also is an unmet need for circuitry to bias cascode transistor circuits which include different kinds of transistors made using different kinds of fabrication sub-technologies which provide the different kinds of transistors with different intrinsic structural characteristics.